1. Technical Field
The present invention generally relates to semiconductor devices and methods of fabricating semiconductor devices, more particularly, to methods of reducing or eliminating gate expansion and maintaining gate critical dimension during source and drain implantation, in a replacement metal gate process.
2. Background Information
In semiconductor device fabrication, replacement gate or replacement metal gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for dummy gate electrodes. In such a process, a sacrificial (or dummy) gate material such as, for instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate material holds the gate position for subsequent metal gate electrodes to be formed. The sacrificial gates are subsequently replaced with, for instance, corresponding replacement metal gates or metal gate electrodes, after source and drain features of the device have been formed.
A goal of integrated circuit fabrication technology is to continue reducing the size of transistors, often employed in integrated circuits or semiconductor devices in order to reduce the size of the resultant devices and thereby provide higher performance, with lower power consumption. This goal includes continuing to provide enhancements to the above-noted gate fabrication approaches, including the replacement metal gate techniques for fabricating a gate structure.